TopSpice 10 Specifications

TopSpice Simulator
Schematic Capture
TopView Graphical Post-Processor
System Requirements
License Activation

TopSpice Simulator

64-bit mixed-mode mixed-signal enhanced version of SPICE circuit simulation program with built-in logic simulator, analog behavioral modeling extensions, PSpicetm and HSPICEtm compatible extensions and many other enhancements. Circuit size is limited only by available system resources.

Input/Output File
TopSpice input format is a text file using the SPICE syntax with extensions for digital simulation and behavioral modeling. TopSpice also accepts most PSpicetm, HSPICEtm and SPICE3 syntax extensions. Output listing is a text file in SPICE2 format. The simulation results data are saved as a compact binary data file.

DC operating bias point, DC sweep, AC linear frequency response, transient response, frequency response analysis (FRA) of switching circuits in the time domain, noise, Fourier harmonic, transfer function, sensitivity, temperature and parametric stepping, "alter" circuit, Monte Carlo and worst case.

Simulator Analysis Commands
Command Description
.AC AC analysis (frequency sweep)
.ALTER Repeat run with altered components
.DC DC sweep
.ENCRYPTED Start of encrypted netlist block
.END End of circuit
.ENDL End of library entry section
.ENDS End of subcircuit definition block
.ENDM End of macromodel definition block
.FOUR Fourier harmonic analysis
.FRA Frequency response analysis (transient nonlinear)
.FUNC Function definition
.GLOBAL Global nodes
.HSPICE$ Enable HSPICE in-line comment marker " $"
.IC Initial condition
.INC Include file
.LIB Model library file
.LOADBIAS Load bias point data file
.MACRO Start macromodel definition block
.MC Monte Carlo analysis
.MODEL Device model definition
.NODESET Set node initial voltages
.NOISE Noise analysis
.OP DC operating point
.OPTIONS Set simulator options
.PARAM Parameter defintion
.PLOT ASCII "line printer" plot
.PRINT Print tabulated simulation data
.PROBE Save simulation results to binary data file
.PROTECT Protect netlist
.RENUMBER Renumber element reference names
.SAVE Save simulation results to binary data file
.SAVEBIAS Save bias point data to file
.SENS Sensitivity analysis
.STAT Device statistical distribution
.STEP Parametric stepping
.SUBCKT Start subcircuit definition block
.TEMP Set operating temperature and repeat run
.TF DC small-signal transfer function calculation
.TRAN Transient analysis
.WC Worst case analysis
.WIDTH Input/output file line width

Built-in Circuit Elements
Resistors, capacitors, inductors, coupled inductors, nonlinear magnetic cores, switches, diodes, BJTs,JFETs, MOSFETs, GaAs FETs, ferroelectric capacitors, ideal and lossy transmission lines, voltage and current sources, controlled sources, digital elements, analog/digital interfaces, and subcircuits (macromodels).

Simulator Built-in Circuit Elements
Device Description
A LTspice special functions
B GaAs FET (GASFET), behavioral source
C Capacitor (linear, ABM expression, POLY, TABLE, PWL, charge expression, FERRO)
D Diode (model levels 0, 1 and 3)
E Voltage-controlled voltage source
F Current-controlled current source (linear, POLY)
G Voltage-controlled current source
H Current-controlled voltage source (linear, POLY)
I Independent current source (AM, EXP, FILE, NOISE, PULSE, PWL, RANDOM, SFAM, SFFM, SIN)
J JFET, GASFET and MESFET (model levels 1, 2, 3 and 6)
K Mutual (coupled) inductance, saturable magnetic core
L Inductor (linear, POLY, PWL, saturable core)
M MOSFET (model levels 1, 2, 3, 7, 8, 14, 44, 49, 53, 54, 55) and VDMOS
O Analog/digital interface
Q BJT (model levels 1, 2, 4)
R Resistor (linear, ABM expression)
S Switch (voltage controlled, VSWITCH and SW models)
T Transmission line (ideal, LTRA, TRN)
U Digital (logic) element
V Independent voltage source (AM, EXP, FILE, PULSE, PWL, RANDOM, SFAM, SFFM, SIN)
X Subcircuit

Simulator Built-in Device Models
Model Description
ATOD Analog-to-digital interface
C Integrated capacitor
CAP Capacitor
CORE Nonlinear magnetic core (Jiles-Atherton model)
D Diode (levels 0, 1 and 3)
DTOA Digital-to-analog interface
FECAP Ferroelectric capacitor
GASFET GaAs FET (levels 1, 2, 3, 6)
LTRA Lossy transmission line
NJF N-channel JFET
NMF N-channel MESFET
NMOS N-channel MOSFET (levels 1, 2, 3, 7, 8, 14, 44, 49, 53, 54, 55)
NPN NPN BJT (levels 1 and 4)
PJF P-channel JFET
PMF P-channel MEFSET
PMOS P-channel MOSFET (levels 1, 2, 3, 7, 8, 14, 44, 49, 53, 54, 55)
PNP PNP BJT (levels 1, 2 and 4)
R Integrated resistor
RES Resistor
SW Switch - voltage-controlled with hysteresis
TRN Lossy transmission line
U3GATE Digital tri-state gates
UALU Digital ALU functions
UCOUNT Digital counter functions
UEFF Digital edge-triggered flip-flops
UGATE Digital Boolean gates and delay function
UGFF Digital gated flip-flops
UIO Analog/digital interface modeling
UPULSE Digital pulse generators
URAM Digital RAM
UROM Digital ROM
USEL Digital decoders, encoders and multiplexers
USREG Digital shift registers
USTIM Digital stimulus generators
VDMOS Vertical double diffused MOSFET
VSWITCH Switch - voltage-controlled (VSWITCH and SW models)

Analog Behavioral Modeling
VALUE (arbitrary expressions of voltage, current, time and temperature), TABLE (look-up tables), FREQ (frequency response and s-parameter tables), LAPLACE (Laplace transforms), POLY (polynomial functions of voltage and current), arbitrary expressions for resistors and capacitors.

FUNC and PARAM statements to define user functions and parameters.

TopSpice support both the PSpice and HSPICE syntax formats for specifying analog behavioral modeling expressions.


Digital Simulation
Built-in event-driven logic simulator; SPICE like syntax for logic elements; nine-state logic simulation; separate analog and digital time step control; no limitations in analog/digital connections; user specified gate delays; user specified A/D interface models; glitch and race condition detection; digital state and waveform output options.

Digital Primitives

Simulator Built-in Digital Primitives
Function Description
ADD N-bit full adder
AND N-input AND gate
BUF Buffer gate(s)
BUF3 Tri-state buffer gate(s)
COMP N-bit magnitude comparator
COUNT N-bit universal counter
DEC N-bit to N-line decoder
DELAY Delay function
DFF Edge-triggered D flip-flop
DIVN Divide-by-N counter
DLATCH Gated D flip-flop (latch)
INV Inverter gate(s)
JKFF Edge-triggered JK flip-flop
MUX One of n-bit multiplexer
NAND N-input NAND gate
NOR N-input NOR gate
OR N-input OR gate
PARITY N-bit parity generator/checker
PENC N-line priority encoder
PSREG N-bit universal shift register (parallel load)
PULSE Pulse generator/multivibrator
RAM Static random-access-memory
ROM Read-only-memory
RSFF Gated RS flip-flop
SREG N-bit shift register (serial in/parallel out)
SREGP N-bit shift register (parallel in/serial out)
SRFF Gated SR flip-flop
SRLATCH SR AND-OR type latch (no invalid states)
XNOR N-input XNOR gate
XOR N-input XOR gate

Signal Sources
AM (amplitude modulated), EXP (exponential), FILE (data file), NOISE (noise generator for .NOISE analysis), PULSE (pulsed waveform), PWL (piecewise linear), RANDOM (random waveform), SFAM (single-frequency AM), SFFM (single-frequency FM), SIN (sine), CLOCK (digital), DATA (digital). Any arbitrary function in time or frequency may also be generated using the behavioral modeling options.

Model libraries
.LIB and .INC commands to search and insert model definitions from model library files. Index search mode for fast searches of multiple or large library files. Compatible with most component vendor and third party model libraries.

The TopSpice software package comes with an extensive set of model libraries with over 35,000 parts. They include discrete devices (diodes, transistors, power semiconductors, etc.), analog ICs and functions, optoelectronic and RF devices, magnetic parts, digital logic families (TTL, CMOS and ECL), SMPS design models, and vendor model libraries.

To view the complete list of models included, browse the Model Library Catalog file (library.txt). Or, download and install the Demo version. Then, open the "Model Library Database" icon in the TopSpice folder, or select "Tools|Model libraries|Model Database" command from either the Schematic Editor or Circuit File Editor menu.

Other Features
Alphanumeric node names, global nodes, user defined parameters and expressions, parameter passing to subcircuits, automatic search of default model libraries, user definable default device models, in-line and multiple comment line markers, simulation status display. Supports TopSpice encrypted model files.

Topview Graphical Post-Processor

TopView is the graphical postprocessor program included with TopSpice for plotting the simulation results and performing waveform analysis. To take full advantage of SPICE simulation results the user must be able to display the results graphically with a minimum of fuss. TopView allows quick and intuitive analysis of the output data in a manner similar as oscilloscopes are used to analyze real electronic circuits.

TopView was specifically designed for rapid viewing of the results for most typical design situations. Unlike other SPICE graphical postprocessor programs, which require the user to go through a cumbersome process of selecting waveforms and plot settings, TopView features fully automated plotting of simulation data. TopView's "Auto Plot" function will read a SPICE output file data, and it will automatically select the appropriate graph settings, assign different plot windows to different variable types such as voltages and currents, determine the units for labeling the axes and plot all the waveforms. To facilitate debugging or tracing of a circuit operation, TopView also includes a "Probe" mode which allows users to interactively pick and plot any waveforms from the simulation data.

Input Format: TopView accepts data from SPICE text output files in the following formats: SPICE2G6, HSPICE(tm), PSpice(tm) and SPICE3. The following data files can also be imported: TopSpice binary output, CSDF, Touchstone s-parameter, .WAV audio and user generated text data files.

Plots: Data points per waveform and number of waveforms in a plot limited only by available system resources (up to 256 million points for a waveform). Data from multiple output files can be displayed on the same plot. Simultaneous display of analog and digital waveforms. Up to eight plots per graph.

Auto/Probe Plotting Modes: users can choose fully automated plotting of simulation results or manual selection of circuit variables. Fast automatic plotting with auto scaling, auto window selection, auto labeling. Auto/manual linear/log scaling of plots. X axis variable selection. Data can be shown as lines, symbols or bars.

Cursors: two cursors are available for reading out waveform values, calculating deltas and slopes, and placing labels anywhere on the plot area. Cursors can be used to find maximum, minimum, peak, RMS, etc. points on waveform. User selectable cursor shapes.

Zoom and scroll: users can zoom-in to any area of the plot, or manually set the axes limits. Then, the plot can be scrolled left-right or up-down.

Waveform operations: any arbitrary expression that can include waveform variable names, constants, arithmetic operator and math functions. Complex vector expressions. Also integration, differentiation and FFT analysis.

Post-processing: instant FFT, histogram plots, "eye" displays, tabulate variable & performance analysis functions.

Plot formats: Bode plots, Smith charts, Nyquist plots, polar charts, eye plots, I-V curves.

Embedded commands: allows TopView postprocessor directive commands to be embedded in SPICE netlist files.

Post-Processor Directives
Command Description
#AUTOPLOT Auto plot specified variables
#AUTOPLOT BODE Bode plot with gain on left axis and phase on right axis
#AUTOPLOT FFT Calculate FFT and plot
#AUTOPLOT NYQUIST Nyquist plot of complex data
#AUTOPLOT POLARCHART Polar chart of complex data
#CALC Calculate expressions
#CALC FFT Calculate FFT
#DATA INTERPOLATEInterpolates data
#DATA LIMITLimits data values
#DATA WINDOWLimits data X range
#MEASURE AREA Measure area (integral) of waveform
#MEASURE DELAY Measure delay
#MEASURE DELTA Measure difference in Y values
#MEASURE FREQ Measure frequency of periodic waveform
#MEASURE MAX Measure maximum value
#MEASURE MEAN Measure mean (average) value
#MEASURE MIN Measure minimum value
#MEASURE RMS Measure RMS value
#MEASURE VALUE Measure value of Y at specified X value
#MEASURE WIDTH Measure X width (pulse, bandwidth, etc.)
#MEASURE XMAX Measure X value at maximum of Y data
#MEASURE XMIN Measure X value at minimum of Y data
#REVISION: Circuit revision info
#RUNSCRIPT Run postprocessor commands in a script file
#SUBTITLE Mark following line as the plot subtitle
#TABULATE Tabulate variable
#WRITEDATA Write plot data to a text file

Output: high quality output to printers. Graphic file export (JPEG, WMF, EMF, BMP, PNG, GIF, TIFF, PDF) option.

Schematic Editor

A graphical schematic entry program is included with TopSpice. It allows the designer to draw electrical circuit schematics from which it generates complete SPICE netlist files automatically. It features:

  • Easy to use graphical user interface. All commands are available through pull-down and pop-up menus and toolbar.

  • Hierarchical designs. Both top-down and bottom-up hierarchical design methodologies are supported. Large design projects can be implemented in multiple levels of hierarchy.

  • Support for SPICE subcircuits (macromodels). The user has options to draw separate subcircuits on a schematic, use SPICE netlist (text) subcircuits, and save subcircuits, or the entire schematic, as SPICE models to a file.

  • Support for schematic with multiple pages. A circuit schematic may be partitioned into a number of separate pages (up to 100).

  • Includes symbols for all the SPICE circuit elements, TopSpice model library parts and many other common components. Users can create and add new schematic symbols using a text editor or the symbol utility functions. Symbols from multiple symbol library files may be used on the same drawing.

  • Extensive symbol attributes options. Most symbols may be rotated, mirrored and/or flipped. No separate definitions are needed for each view. Option to draw symbols at twice normal size. Symbol "preview" box for quick part selection. Option to draw symbols at twice normal size.

  • Snap-to-grid, automatic part numbering and "double-click" to repeat part for fast placement of components.

  • "Auto-junction" and orthogonal drawing constraint modes for easy wiring connections.

  • Complete edit commands include cut, paste, copy, move, rotate, mirror, flip and change attributes. Double-click to edit any object attribute on the drawing. Edit operations can be applied to a group, area, subcircuit or entire schematic.

  • Advanced wire "rubberbanding" feature maintains both electrical connectivity and aesthetic appearance when moving parts on a schematic.

  • Node names may be given to wires and part pins by placing a label next to it. The assigned node name is used in the SPICE netlist file instead of a node number.

  • Easy schematic navigation with position scroll bars, multiple zoom levels, area zooming, hierarchical block "push-down" and many convenient keyboard shortcuts. Full page display option for any sheet size (A through E).

  • Auto symbol generator function automatically creates schematic symbols to match any subcircuit block.

  • Fast and user transparent generation of complete SPICE circuit files. SPICE commands, models, etc. may be included in a separate command file, which is automatically inserted to the SPICE netlist, or they may also be added directly on the schematic as text objects.

  • Option to show SPICE node numbers on schematic. Automatic connection of same name wires, pins, power rails and ground.

  • Full support for SPICE syntax including specification of device and source parameters, and subcircuits.

  • Support for TopSpice digital functions and analog behavioral models.

  • Probe circuit function allows the user to use a virtual probe to interactively point to a schematic wire or part and display the simulated waveforms or operating point bias values.

  • DC bias operating point node voltages, currents and device power display on the schematic drawing. Option to highligh devices that exceed maximum current or power specifications.

  • Selection "disable" feature to remove temporarily components from the simulation circuit without modifying the schematic drawing for convenient debugging and design analysis.

  • "Auto save" feature automatically saves changes at user specified intervals.

  • User set configuration settings, zoom level and cursor position are saved and restored when editing the same schematic for quick design iterations.

  • Automatic updating of title block information.

  • Model file encryption tool.

  • Model import tool converts SPICE models, IBIS models and s-parameter data files into schematic parts.

  • Support for multiple/parallel simulation runs of the same schematic circuit.

  • Drawing using graphics objects.

  • Insert picture files as schematic objects allows for convenient documentation.

  • High quality hard copy to most printers. Any sheet size may be printed on any paper size. Graphic file (JPEG, WMF, EMF, BMP, PNG, GIF, TIFF, PDF) export option.

System Requirements

TopSpice is a Windows 64-bit application. Requirements:

  • Windows 64-bit operating system (7 SP1*, 8, 10 or 11).
  • PC with Intel Core or compatible multi-core CPU.
  • 1GB RAM minimum.
  • 500MB free disk drive space.
  • Display with 1200x800 minimum screen resolution.
  • Internet connection or email service.

All TopSpice products require online license activation (offline activation option also available) for each installation.

* Windows 7 with Service Pack 1 update.

Product specifications are subject to change without notice. All company and product names are trademarks or registered trademarks of their respective holders.


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